By Douglas E. Ott
A Designer's advisor to VHDL Synthesis is meant for either layout engineers who are looking to use VHDL-based common sense synthesis ASICs and for managers who have to achieve a realistic realizing of the problems eager about utilizing this know-how. The emphasis is positioned extra on sensible functions of VHDL and synthesis in accordance with real reports, instead of on a extra theoretical method of the language.
VHDL and good judgment synthesis instruments supply very strong functions for ASIC layout, yet also are very complicated and characterize an intensive departure from conventional layout equipment. this case has made it tough to start in utilizing this expertise for either designers and administration, due to the fact a tremendous studying attempt and `culture' switch is needed. A Designer's consultant to VHDL Synthesis has been written to assist layout engineers and different pros effectively make the transition to a layout technique according to VHDL and log synthesis rather than the extra conventional schematic established technique. whereas there are many texts at the VHDL language and its use in simulation, little has been written from a designer's perspective on the right way to use VHDL and common sense synthesis to layout actual ASIC structures. the cloth during this ebook is predicated on adventure received in effectively utilizing those thoughts for ASIC layout and is based seriously on practical examples to illustrate the rules concerned.
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Additional resources for A Designer’s Guide to VHDL Synthesis
The major commercial VHDL logic synthesis systems nonnally accept RTL level deSCriptions as input to the design process, and the design techniques used to synthesize logic will be covered in great detail in succeeding chapters of this book. Structural Level This syntax of VHDL coding is similar to the use of a netlist, which shows the design as a structure consisting of "components" interconnected by signals. The components can be as simple as gates and flip flops or can be larger blocks described as behavioral or RTL level code, and VHDL allows any mix of these styles to be used simultaneously in an overall design.
It is prudent to run the synthesis tools briefly on a design even before the VHDL simulations are complete just to check that the code is synthesizable and no other problems are found that could cause you to have to rework the VHDL description. The reason this could happen is that every synthesis system has some limitations on the VHDL code it can synthesize into logic, even though the code may simulate perfectly well. Fortunately a number of the commercial VHDL simulators can do synthesis guideline checking during the compilation process which reduces the need for the additional check.
Other less global test and simulation issues affect how ASIC logic is designed and are normally part of the design-for-test rules. For example, if a 24 bit binary counter is needed, it will take 224 clocks to count through all of its states and verify that the circuit works correctly in the ASIC. Since this would take an enormous amount of time to simulate, and would likely exceed the ASIC tester's capacity, a typical design practice is to break the counter into smaller sections to allow testing with a smaller number of clocks, or to provide a means for presetting the counter to a desired state.
A Designer’s Guide to VHDL Synthesis by Douglas E. Ott